EP2A25F672I9 vs EP2A25F672I6 Vergleich

Detaillierter Direktvergleich von EP2A25F672I9 von Intel und EP2A25F672I6 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP2A25F672I9 EP2A25F672I6
Marke Intel Intel
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete NRND
Lagerstatus In Stock In Stock
Stückpreis (USD) $135,00 $178,00
Family APEX II APEX II
Manufacturer Intel (formerly Altera) —
Logic Elements (LEs) 24,320 —
System Gates (typical) 900,000 —
Maximum Operating Frequency 236 MHz —
Process Technology 0.15 µm CMOS 0.18 µm CMOS
Core Voltage (VCCINT) 1.5 V —
Gehäuse 672-pin FC-FBGA 672-ball FineLine BGA (FBGA-672)
Pin-Anzahl 672 —
Temperature Grade Industrial (-40 °C to +100 °C) Industrial (-40 °C to +100 °C ambient)
Speed Grade 9 (fastest APEX II grade) 6
Embedded System Blocks (ESBs) Yes (dual-port RAM/ROM) —
Maximum User I/O [DATA_NEEDED: max user I/O pin count] —
Maximum Memory Bits 422,400 bits —
PLLs 4 —
Montageart Surface Mount (flip-chip BGA) Surface Mount (BGA)
Peak Reflow Temperature 220 °C (per distributor listing) —
Feuchtigkeitsempfindlichkeitsgrad (MSL) 3 —
RoHS-Status Unknown (legacy 2000s part; verify lot certificate) [DATA_NEEDED: RoHS compliance status]
Logic Elements (typical gates) — 25,000
Fabric Architecture — SRAM-based LUT
Core Voltage — 1.5 V
Configuration Method — External SRAM configuration device (EPC series)
Embedded Memory — Embedded System Blocks (ESB), dual-port RAM / CAM
DSP Blocks — MultiCore dedicated multipliers
Boundary Scan — JTAG (IEEE 1149.1) compliant
Clock Management — Dedicated PLL / clock tree circuitry
I/O Bank Count — [DATA_NEEDED: number of user I/O banks]
Lead-Free — [DATA_NEEDED: lead-free status]
MSL-Level — [DATA_NEEDED: moisture sensitivity level]

Datenblätter & Ressourcen

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