EP2A25F672I9 vs EP2A25F672I6 Comparaison
Comparaison détaillée côte à côte de EP2A25F672I9 par Intel et EP2A25F672I6 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP2A25F672I9 | EP2A25F672I6 |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $135,00 | $178,00 |
| Family | APEX II | APEX II |
| Manufacturer | Intel (formerly Altera) | — |
| Logic Elements (LEs) | 24,320 | — |
| System Gates (typical) | 900,000 | — |
| Maximum Operating Frequency | 236 MHz | — |
| Process Technology | 0.15 µm CMOS | 0.18 µm CMOS |
| Core Voltage (VCCINT) | 1.5 V | — |
| Boîtier | 672-pin FC-FBGA | 672-ball FineLine BGA (FBGA-672) |
| Nombre de broches | 672 | — |
| Temperature Grade | Industrial (-40 °C to +100 °C) | Industrial (-40 °C to +100 °C ambient) |
| Speed Grade | 9 (fastest APEX II grade) | 6 |
| Embedded System Blocks (ESBs) | Yes (dual-port RAM/ROM) | — |
| Maximum User I/O | [DATA_NEEDED: max user I/O pin count] | — |
| Maximum Memory Bits | 422,400 bits | — |
| PLLs | 4 | — |
| Type de montage | Surface Mount (flip-chip BGA) | Surface Mount (BGA) |
| Peak Reflow Temperature | 220 °C (per distributor listing) | — |
| Niveau de sensibilité à l'humidité (MSL) | 3 | — |
| Statut RoHS | Unknown (legacy 2000s part; verify lot certificate) | [DATA_NEEDED: RoHS compliance status] |
| Logic Elements (typical gates) | — | 25,000 |
| Fabric Architecture | — | SRAM-based LUT |
| Core Voltage | — | 1.5 V |
| Configuration Method | — | External SRAM configuration device (EPC series) |
| Embedded Memory | — | Embedded System Blocks (ESB), dual-port RAM / CAM |
| DSP Blocks | — | MultiCore dedicated multipliers |
| Boundary Scan | — | JTAG (IEEE 1149.1) compliant |
| Clock Management | — | Dedicated PLL / clock tree circuitry |
| I/O Bank Count | — | [DATA_NEEDED: number of user I/O banks] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Niveau MSL | — | [DATA_NEEDED: moisture sensitivity level] |