EP2A70B724I-8 vs EP2A70B724C8N Vergleich
Detaillierter Direktvergleich von EP2A70B724I-8 von Altera und EP2A70B724C8N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EP2A70B724C8N - APEX II FPGA, 3M Gates, 724-FCBGA | Altera / Intel
EP2A70B724C8N ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EP2A70B724I-8 | EP2A70B724C8N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $119,00 | $240,00 |
| Family | APEX II | FPGA (PLD) |
| Logic Elements / Cells | 67,200 cells | 67,200 |
| System Gates | 3,000,000 | 3,000,000 (3 M) |
| Maximum Internal Frequency | 281 MHz | — |
| Process Technology | 0.15 µm CMOS | 0.15 um CMOS, SRAM-based |
| Core Supply Voltage | 1.5 V | 1.5 V |
| I/O Supply Voltage | 3.3 V | — |
| Anzahl der Pins | 724 | — |
| Package Type | FCBGA (Flip-Chip Ball Grid Array) | FCBGA-724 (square) |
| Betriebstemperatur | -40 °C to +100 °C (Industrial) | — |
| Peak Reflow Temperature | 220 °C (per JEDEC J-STD-020) | — |
| User I/O Banks | [DATA_NEEDED: user I/O bank count] | — |
| User I/O Pins | [DATA_NEEDED: user I/O pin count] | — |
| Embedded System Blocks (ESBs) | [DATA_NEEDED: ESB count] | — |
| Embedded Array Blocks (EABs) | [DATA_NEEDED: EAB count] | — |
| Embedded RAM | [DATA_NEEDED: total bits] | — |
| PLLs | [DATA_NEEDED: PLL count] | — |
| Configuration Method | JTAG / Passive Serial / Passive Parallel | — |
| Montageart | Surface Mount | Surface Mount (BGA) |
| MSL-Level | [DATA_NEEDED: MSL level] | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance] | — |
| Series | — | APEX II (EP2A70) |
| Macrocells | — | 16 |
| Product Terms | — | 32 |
| Propagation Delay | — | 2.49 ns |
| Maximum Internal Clock Frequency | — | 281 MHz |
| Maximum Clock Frequency (fMAX) | — | 1694.91 MHz |
| Architecture | — | PLA-type / LUT-based |
| Number of Pins / Balls | — | 724 |
| Terminal Pitch | — | 1.270 mm |
| Maximum User I/O | — | 536 |