EP2A70B724I-8 vs EP2A70B724C8N Comparaison
Comparaison détaillée côte à côte de EP2A70B724I-8 par Altera et EP2A70B724C8N par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EP2A70B724C8N - APEX II FPGA, 3M Gates, 724-FCBGA | Altera / Intel
EP2A70B724C8N ⚠ Dernier achatComparaison des spécifications
| Paramètre | EP2A70B724I-8 | EP2A70B724C8N |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $119,00 | $240,00 |
| Family | APEX II | FPGA (PLD) |
| Logic Elements / Cells | 67,200 cells | 67,200 |
| System Gates | 3,000,000 | 3,000,000 (3 M) |
| Maximum Internal Frequency | 281 MHz | — |
| Process Technology | 0.15 µm CMOS | 0.15 um CMOS, SRAM-based |
| Core Supply Voltage | 1.5 V | 1.5 V |
| I/O Supply Voltage | 3.3 V | — |
| Nombre de broches | 724 | — |
| Package Type | FCBGA (Flip-Chip Ball Grid Array) | FCBGA-724 (square) |
| Température de fonctionnement | -40 °C to +100 °C (Industrial) | — |
| Peak Reflow Temperature | 220 °C (per JEDEC J-STD-020) | — |
| User I/O Banks | [DATA_NEEDED: user I/O bank count] | — |
| User I/O Pins | [DATA_NEEDED: user I/O pin count] | — |
| Embedded System Blocks (ESBs) | [DATA_NEEDED: ESB count] | — |
| Embedded Array Blocks (EABs) | [DATA_NEEDED: EAB count] | — |
| Embedded RAM | [DATA_NEEDED: total bits] | — |
| PLLs | [DATA_NEEDED: PLL count] | — |
| Configuration Method | JTAG / Passive Serial / Passive Parallel | — |
| Type de montage | Surface Mount | Surface Mount (BGA) |
| Niveau MSL | [DATA_NEEDED: MSL level] | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance] | — |
| Series | — | APEX II (EP2A70) |
| Macrocells | — | 16 |
| Product Terms | — | 32 |
| Propagation Delay | — | 2.49 ns |
| Maximum Internal Clock Frequency | — | 281 MHz |
| Maximum Clock Frequency (fMAX) | — | 1694.91 MHz |
| Architecture | — | PLA-type / LUT-based |
| Number of Pins / Balls | — | 724 |
| Terminal Pitch | — | 1.270 mm |
| Maximum User I/O | — | 536 |