EP2A70B724I-8 vs EP2A70B724C8N Comparison

Detailed side-by-side comparison of EP2A70B724I-8 by Altera and EP2A70B724C8N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP2A70B724I-8 EP2A70B724C8N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Last Time Buy
Family APEX II FPGA (PLD)
Logic Elements / Cells 67,200 cells 67,200
System Gates 3,000,000 3,000,000 (3 M)
Maximum Internal Frequency 281 MHz —
Process Technology 0.15 µm CMOS 0.15 um CMOS, SRAM-based
Core Supply Voltage 1.5 V 1.5 V
I/O Supply Voltage 3.3 V —
Number of Pins 724 —
Package Type FCBGA (Flip-Chip Ball Grid Array) FCBGA-724 (square)
Operating Temperature -40 °C to +100 °C (Industrial) —
Peak Reflow Temperature 220 °C (per JEDEC J-STD-020) —
User I/O Banks [DATA_NEEDED: user I/O bank count] —
User I/O Pins [DATA_NEEDED: user I/O pin count] —
Embedded System Blocks (ESBs) [DATA_NEEDED: ESB count] —
Embedded Array Blocks (EABs) [DATA_NEEDED: EAB count] —
Embedded RAM [DATA_NEEDED: total bits] —
PLLs [DATA_NEEDED: PLL count] —
Configuration Method JTAG / Passive Serial / Passive Parallel —
Mounting Type Surface Mount Surface Mount (BGA)
MSL Level [DATA_NEEDED: MSL level] —
RoHS Status [DATA_NEEDED: RoHS compliance] —
Series — APEX II (EP2A70)
Macrocells — 16
Product Terms — 32
Propagation Delay — 2.49 ns
Maximum Internal Clock Frequency — 281 MHz
Maximum Clock Frequency (fMAX) — 1694.91 MHz
Architecture — PLA-type / LUT-based
Number of Pins / Balls — 724
Terminal Pitch — 1.270 mm
Maximum User I/O — 536

Datasheets & Resources

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