EP2C8F256C8N vs EP2C5F256C8N Vergleich
Detaillierter Direktvergleich von EP2C8F256C8N von Altera und EP2C5F256C8N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EP2C5F256C8N - Cyclone II FPGA, 4.6K LEs, 158 I/O | Altera / Intel
EP2C5F256C8N ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EP2C8F256C8N | EP2C5F256C8N |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $0,00 | $11,84 |
| Product Type | Field Programmable Gate Array (FPGA) | — |
| Product Family | Cyclone II | — |
| Logic Elements | 8256 | — |
| Embedded Memory | 165888 bit | — |
| Programmable I/O Count | 182 | — |
| Gehäuse | 256-LBGA | 256-ball FineLine BGA (FBGA-256) |
| Package Pin Count | 256 pin | — |
| Versorgungsspannung | 3.3 V | — |
| Maximum Frequency | 156 MHz | — |
| RoHS-Status | unknown | Compliant (lead-free) |
| REACH Status | unknown | — |
| AEC-Q100 Qualification | unknown | — |
| Lead-Free Status | unknown | — |
| Halogen-Free Status | unknown | — |
| Betriebstemperaturbereich | [DATA_NEEDED: operating temperature range] | — |
| Configuration Interface | [DATA_NEEDED: configuration interface] | — |
| I/O Standard Support | [DATA_NEEDED: supported I/O standards] | — |
| Core Voltage Range | [DATA_NEEDED: core voltage range] | — |
| Family | — | Cyclone II |
| Logic Elements (LE) | — | 4,608 |
| Logic Array Blocks (LAB) | — | 288 |
| Embedded Memory (M4K blocks) | — | 119,808 bits (~14.6 Kbytes) |
| Embedded 18x18 Multipliers | — | 13 |
| PLLs | — | 2 |
| Maximum User I/O Pins | — | 158 |
| Process Technology | — | 90 nm low-k CMOS |
| Core Voltage | — | 1.2 V |
| Speed Grade | — | 8 (commercial) |
| Betriebstemperatur | — | 0C to +85C (commercial) |
| Montageart | — | Surface Mount |
| Configuration Method | — | SRAM, JTAG (IEEE 1149.1), Passive Serial |
| MSL-Level | — | [DATA_NEEDED: MSL level per JEDEC J-STD-020] |