EP2SGX130GF40C5ES vs EP2SGX130GF40C4NES Vergleich

Detaillierter Direktvergleich von EP2SGX130GF40C5ES von Altera und EP2SGX130GF40C4NES von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Altera
EP2SGX130GF40C5ES EP2SGX130GF40C5ES - Stratix II GX 132K LC FPGA, FC-FBGA-1508 | Altera

EP2SGX130GF40C5ES - Stratix II GX 132K LC FPGA, FC-FBGA-1508 | Altera

EP2SGX130GF40C5ES ⚠ Letzte Bestellmöglichkeit
Intel
EP2SGX130GF40C4NES EP2SGX130GF40C4NES - 132K LE Stratix II GX FPGA, 6.375Gbps SERDES, 1508-FBGA | Intel

EP2SGX130GF40C4NES - 132K LE Stratix II GX FPGA, 6.375Gbps SERDES, 1508-FBGA | Intel

EP2SGX130GF40C4NES ⚠ Letzte Bestellmöglichkeit

Spezifikationsvergleich

Parameter EP2SGX130GF40C5ES EP2SGX130GF40C4NES
Marke Altera Intel
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Letzte Kaufgelegenheit Letzte Kaufgelegenheit
Lagerstatus In Stock In Stock
Stückpreis (USD) $1.380,00 $1.380,00
Family Stratix II GX Stratix II GX
Logic Elements 132,540 132,540
Logic Array Blocks (LABs) 7,047 —
Internal Frequency (max) 609.76 MHz —
Process Technology 90 nm CMOS 90 nm CMOS
Core Supply Voltage (nominal) 1.2 V —
Speed Grade C5 (mid-upper) C4 (speed grade -4)
Betriebstemperatur 0C to +85C (Commercial Extended) Commercial Extended (per N suffix)
Gehäuse FC-FBGA-1508 (40 x 40 mm, 1 mm pitch) —
Ball Count 1508 —
Package Type Flip-Chip Fine-pitch BGA —
Montageart Surface Mount Surface Mount (flip-chip BGA)
Lead-Free / Halogen-Free Yes (G suffix) —
RoHS-Status Compliant —
Configuration Interface JTAG / Passive Serial / Active Serial —
Logic Blocks / ALMs — Approximately 53,000 ALMs
Core Voltage — 1.2 V
Maximum Transceiver Data Rate — 6.375 Gbps
Transceiver Channels — Up to 20 (4 to 20, device-dependent)
User I/O Pins — 734
Total Package Pins — 1508 (FC-FBGA ball grid)
Package Code — GF40 (FC-FBGA, 40x40 mm, 1.0 mm pitch)
Internal Operating Frequency — Up to 717 MHz
Embedded Memory — Approximately 4.5 Mbits (TriMatrix)
PLL Blocks — 8
DSP Blocks — Yes (variable, see datasheet)
Lead-Free / RoHS — Yes (LEAD FREE per datasheet family code)
MSL-Level — Per JEDEC J-STD-020, typically MSL-4 or higher [DATA_NEEDED: exact MSL level]
JEDEC Standard Reference — MS-034AAU-1

Datenblätter & Ressourcen

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