EP3SL200H780C4L vs EP3SL200H780I4L Vergleich
Detaillierter Direktvergleich von EP3SL200H780C4L von Intel und EP3SL200H780I4L von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP3SL200H780C4L | EP3SL200H780I4L |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $6.459,35 | $1.395,00 |
| Manufacturer | Intel (formerly Altera) | — |
| Series | Stratix III | — |
| Device Type | FPGA - Field Programmable Gate Array | — |
| Logic Elements | 200,000 | 200,000 |
| Embedded Memory | 6.5 Mbit | — |
| User I/O Count | 488 | — |
| Package Type | 780-ball FCBGA (FineLine BGA, HBGA) | — |
| Package Code | BGA-780 / PBGA780 / HBGA-780 | — |
| Package Mounting | Surface Mount | — |
| Internal Logic Frequency | up to 717 MHz (per ampheo datasheet brief) | — |
| Speed Grade | -4 (medium performance, commercial) | I4 (Industrial) |
| Betriebstemperatur | 0C to 85C (commercial) | -40C to +100C (Industrial) |
| Lead-Free / Pb-Free | Yes (L suffix, lead-free) | — |
| RoHS-Status | Compliant | Compliant |
| Process Technology | TSMC 40 nm | 65 nm CMOS |
| Configuration Modes | FPP, AS, PS, JTAG | — |
| Family | — | Stratix III L |
| Logic Array Blocks (LABs) | — | 8,000 |
| Embedded Memory (Bits) | — | 10,901,504 |
| Maximum User I/O | — | 488 |
| Core Supply Voltage | — | 0.86 V to 1.15 V |
| Internal Performance | — | 375 MHz |
| Gehäuse | — | 780-pin FC-HFBGA (Flip-Chip) |
| Montageart | — | Surface Mount |
| Transceivers | — | Up to 24 channels |
| Transceiver Data Rate | — | Up to 6.375 Gbps |
| DSP Blocks | — | 9x9 / 18x18 / 36x36 multipliers |
| Memory Interface Support | — | DDR3, DDR2, DDR, QDR II+, RLDRAM II |
| JTAG Support | — | IEEE Std 1149.1 Boundary-Scan |
| HardCopy Support | — | Compatible (Lattice-style migration path via HardCopy III) |