EP610DC15 vs EP610DC35 Vergleich
Detaillierter Direktvergleich von EP610DC15 von Intel und EP610DC35 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP610DC15 | EP610DC35 |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $7,50 | $19,20 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | EP610 Classic EPLD | Classic EPLD |
| Macrocells | 16 | — |
| Architecture | PAL-type | — |
| Propagation Delay (tPD) | 15 ns | 35 ns |
| Maximum Clock Frequency (fMAX) | 71.4 MHz | — |
| Pipelined Data Rate | up to 100 MHz | up to 100 MHz |
| Total Inputs | 20 | — |
| I/O Lines | 16 | — |
| Product Terms | 160 | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Technology | CMOS | UV-erasable CMOS EPROM |
| Betriebstemperatur | 0C to +70C | [DATA_NEEDED: operating temperature range] |
| Gehäuse | 24-pin CDIP (Ceramic DIP, windowed) | 24-pin CDIP (Ceramic DIP) with quartz erase window |
| Montageart | Through-Hole | Through-Hole |
| Reprogrammability | Yes (UV erasable via windowed package) | — |
| RoHS-Status | unknown | [DATA_NEEDED: RoHS status] |
| Logic Elements | — | 16 macrocells |
| Usable Gates | — | 300 |
| Maximum Frequency | — | 28.6 MHz |
| Versorgungsspannung | — | 5 V |
| Pin-Anzahl | — | 24 |
| Programming Method | — | Altera legacy programmer (PLDLMax or compatible) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| I/O Pins | — | [DATA_NEEDED: number of user I/O pins] |