EP610DC15 vs EP610DC35 Comparación
Comparación detallada lado a lado de EP610DC15 por Intel y EP610DC35 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP610DC15 | EP610DC35 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $7,50 | $19,20 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | EP610 Classic EPLD | Classic EPLD |
| Macrocells | 16 | — |
| Architecture | PAL-type | — |
| Propagation Delay (tPD) | 15 ns | 35 ns |
| Maximum Clock Frequency (fMAX) | 71.4 MHz | — |
| Pipelined Data Rate | up to 100 MHz | up to 100 MHz |
| Total Inputs | 20 | — |
| I/O Lines | 16 | — |
| Product Terms | 160 | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Technology | CMOS | UV-erasable CMOS EPROM |
| Temperatura de funcionamiento | 0C to +70C | [DATA_NEEDED: operating temperature range] |
| Encapsulado | 24-pin CDIP (Ceramic DIP, windowed) | 24-pin CDIP (Ceramic DIP) with quartz erase window |
| Tipo de montaje | Through-Hole | Through-Hole |
| Reprogrammability | Yes (UV erasable via windowed package) | — |
| Estado RoHS | unknown | [DATA_NEEDED: RoHS status] |
| Logic Elements | — | 16 macrocells |
| Usable Gates | — | 300 |
| Maximum Frequency | — | 28.6 MHz |
| Tensión de alimentación | — | 5 V |
| Recuento de pines | — | 24 |
| Programming Method | — | Altera legacy programmer (PLDLMax or compatible) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| I/O Pins | — | [DATA_NEEDED: number of user I/O pins] |