EP610LC-35 vs EP610LC-30 Vergleich
Detaillierter Direktvergleich von EP610LC-35 von Altera und EP610LC-30 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP610LC-35 | EP610LC-30 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,95 | $16,40 |
| Family | Altera Classic EPLD | Classic EPLD (EP610) |
| Device Series | EP610 | — |
| Macrocells | 16 | — |
| Usable Gates | 300 | — |
| Propagation Delay (tpd) | 37 ns | — |
| Supply Voltage (Vcc) | 5 V | — |
| Technology | CMOS EEPROM (one-time-programmable plastic) | CMOS EPROM (UV-erasable) |
| Gehäuse | 28-pin PLCC (J-lead) | 24-pin CERDIP / PDIP |
| Betriebstemperatur | Commercial (0C to +70C) [DATA_NEEDED: exact grade letter] | 0 C to +70 C (commercial) / -55 C to +125 C (military) |
| Speed Grade | -35 (slowest EP610) | — |
| Montageart | Surface Mount | Through-Hole |
| Programmable Pins | 24 input / 16 output (shared macrocells) | — |
| RoHS-Status | [DATA_NEEDED: rohs_status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead_free] | — |
| MSL-Level | [DATA_NEEDED: msl_level] | — |
| Programming Tool | MAX+PLUS II development system | — |
| Macro Cells | — | 16 |
| Logic Gates | — | Equivalent to 300 gates (typical) |
| Pin-to-Pin Delay (tPD) | — | 30 ns |
| Pipelined Data Rate | — | up to 100 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Programming Voltage (VPP) | — | 13 V nominal |
| Erase/Program Cycles | — | 1000 typical |
| Ausgangstyp | — | CMOS tri-state (programmable) |
| Logic Compatibility | — | TTL and CMOS |
| Turbo Mode | — | Yes (registered path bypass) |