EP610LC-35 vs EP610LC-30 Comparaison
Comparaison détaillée côte à côte de EP610LC-35 par Altera et EP610LC-30 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP610LC-35 | EP610LC-30 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9,95 | $16,40 |
| Family | Altera Classic EPLD | Classic EPLD (EP610) |
| Device Series | EP610 | — |
| Macrocells | 16 | — |
| Usable Gates | 300 | — |
| Propagation Delay (tpd) | 37 ns | — |
| Supply Voltage (Vcc) | 5 V | — |
| Technology | CMOS EEPROM (one-time-programmable plastic) | CMOS EPROM (UV-erasable) |
| Boîtier | 28-pin PLCC (J-lead) | 24-pin CERDIP / PDIP |
| Température de fonctionnement | Commercial (0C to +70C) [DATA_NEEDED: exact grade letter] | 0 C to +70 C (commercial) / -55 C to +125 C (military) |
| Speed Grade | -35 (slowest EP610) | — |
| Type de montage | Surface Mount | Through-Hole |
| Programmable Pins | 24 input / 16 output (shared macrocells) | — |
| Statut RoHS | [DATA_NEEDED: rohs_status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead_free] | — |
| Niveau MSL | [DATA_NEEDED: msl_level] | — |
| Programming Tool | MAX+PLUS II development system | — |
| Macro Cells | — | 16 |
| Logic Gates | — | Equivalent to 300 gates (typical) |
| Pin-to-Pin Delay (tPD) | — | 30 ns |
| Pipelined Data Rate | — | up to 100 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Programming Voltage (VPP) | — | 13 V nominal |
| Erase/Program Cycles | — | 1000 typical |
| Type de sortie | — | CMOS tri-state (programmable) |
| Logic Compatibility | — | TTL and CMOS |
| Turbo Mode | — | Yes (registered path bypass) |