EP610LC-35 vs EP610LC-30 비교
다음의 상세 나란히 비교: EP610LC-35 제조: Altera 및 EP610LC-30 제조: Intel. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP610LC-35 | EP610LC-30 |
|---|---|---|
| 브랜드 | Altera | Intel |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $9.95 | $16.40 |
| Family | Altera Classic EPLD | Classic EPLD (EP610) |
| Device Series | EP610 | — |
| Macrocells | 16 | — |
| Usable Gates | 300 | — |
| Propagation Delay (tpd) | 37 ns | — |
| Supply Voltage (Vcc) | 5 V | — |
| Technology | CMOS EEPROM (one-time-programmable plastic) | CMOS EPROM (UV-erasable) |
| 패키지 | 28-pin PLCC (J-lead) | 24-pin CERDIP / PDIP |
| 동작 온도 | Commercial (0C to +70C) [DATA_NEEDED: exact grade letter] | 0 C to +70 C (commercial) / -55 C to +125 C (military) |
| Speed Grade | -35 (slowest EP610) | — |
| 실장 유형 | Surface Mount | Through-Hole |
| Programmable Pins | 24 input / 16 output (shared macrocells) | — |
| RoHS 상태 | [DATA_NEEDED: rohs_status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead_free] | — |
| MSL 레벨 | [DATA_NEEDED: msl_level] | — |
| Programming Tool | MAX+PLUS II development system | — |
| Macro Cells | — | 16 |
| Logic Gates | — | Equivalent to 300 gates (typical) |
| Pin-to-Pin Delay (tPD) | — | 30 ns |
| Pipelined Data Rate | — | up to 100 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Programming Voltage (VPP) | — | 13 V nominal |
| Erase/Program Cycles | — | 1000 typical |
| 출력 유형 | — | CMOS tri-state (programmable) |
| Logic Compatibility | — | TTL and CMOS |
| Turbo Mode | — | Yes (registered path bypass) |