EP610LI-35 vs EP610DC-35 Vergleich
Detaillierter Direktvergleich von EP610LI-35 von Altera und EP610DC-35 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP610LI-35 | EP610DC-35 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $10,50 | $18,40 |
| Family | Classic EPLD | Altera Classic EP610 |
| Series | EP610 | — |
| Number of Macrocells | 16 | — |
| Usable Gates | 300 | 300 |
| Number of I/O Pins | 16 | — |
| Total Inputs | 20 | — |
| Dedicated Inputs | 4 | — |
| External Clock Inputs | 2 | — |
| Product Terms | 160 | — |
| Maximum Propagation Delay | 35 ns (tpd) | — |
| Maximum Operating Frequency | 28.6 MHz (fmax) | — |
| Pipelined Data Rate | Up to 100 MHz | up to 100 MHz |
| Versorgungsspannung | 5 V | — |
| Process Technology | CMOS | CMOS |
| Architecture | PAL-type (AND-OR array) | — |
| Gehäuse | 28-pin PLCC (windowed ceramic, 'LI') | 24-pin CDIP (windowed CERDIP) 0.300 inch |
| Betriebstemperaturbereich | [DATA_NEEDED: military/industrial operating temperature range] | — |
| Programming Technology | UV-erasable (EPROM) | — |
| Montageart | Surface Mount | Through-Hole (DIP) |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] |
| Device Type | — | CPLD - Classic EPLD |
| Macrocells | — | 16 |
| Propagation Delay (tPD) | — | 35 ns |
| Maximum Frequency (fMAX) | — | 28.6 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Program/erase Method | — | UV-erasable (windowed CERDIP) |
| Betriebstemperatur | — | 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] |
| Manufacturer | — | Originally Altera; today supplied via Rochester Electronics (authorized) |