EP610PC-20 vs EP610DC-20 Vergleich
Detaillierter Direktvergleich von EP610PC-20 von Altera und EP610DC-20 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP610PC-20 | EP610DC-20 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $47,80 | $15,85 |
| Family | Classic EPLD | Classic EP610 |
| Logic Elements | 16 macrocells | — |
| Usable Gates | 300 | — |
| Propagation Delay (tPD) | 20 ns | 22 ns |
| Maximum Operating Frequency | 100 MHz (pipelined) | — |
| Supply Voltage (VCC) | 5 V ±10% | 4.75 V to 5.25 V (5 V nominal) |
| Anzahl der Pins | 24 | — |
| Gehäuse | PDIP-24 | 24-pin Ceramic DIP (CDIP-24) with UV window |
| Betriebstemperatur | 0C to +70C (commercial) | 0 °C to 70 °C (commercial) |
| Process Technology | CMOS EPROM | CMOS, UV-erasable floating gate |
| Programmable Flip-Flops | 16 | — |
| Input Pins | 24 | — |
| Output Pins | 16 | — |
| I/O Compatibility | TTL | — |
| Program/Erase Method | UV (windowed) or OTP | — |
| RoHS-Status | Non-compliant (legacy PDIP) | [DATA_NEEDED: RoHS compliance status] |
| Product Type | — | CMOS UV-Erasable Programmable Logic Device (EPLD) |
| Logic Macrocells | — | 16 |
| Dedicated Inputs | — | 4 |
| I/O Pins | — | 16 (bidirectional) |
| Total Usable Pins | — | 20 |
| Product Terms (p-terms) | — | 160 |
| Maximum Toggle Frequency (fMAX) | — | 55.6 MHz |
| Programming Method | — | UV erasure + parallel programmer |
| Montageart | — | Through-hole |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |