EP610PC-20 vs EP610DC-20 对比
详细并排对比 EP610PC-20 出自 Altera 和 EP610DC-20 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP610PC-20 | EP610DC-20 |
|---|---|---|
| 品牌 | Altera | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $47.80 | $15.85 |
| Family | Classic EPLD | Classic EP610 |
| Logic Elements | 16 macrocells | — |
| Usable Gates | 300 | — |
| Propagation Delay (tPD) | 20 ns | 22 ns |
| Maximum Operating Frequency | 100 MHz (pipelined) | — |
| Supply Voltage (VCC) | 5 V ±10% | 4.75 V to 5.25 V (5 V nominal) |
| 引脚数 | 24 | — |
| 封装 | PDIP-24 | 24-pin Ceramic DIP (CDIP-24) with UV window |
| 工作温度 | 0C to +70C (commercial) | 0 °C to 70 °C (commercial) |
| Process Technology | CMOS EPROM | CMOS, UV-erasable floating gate |
| Programmable Flip-Flops | 16 | — |
| Input Pins | 24 | — |
| Output Pins | 16 | — |
| I/O Compatibility | TTL | — |
| Program/Erase Method | UV (windowed) or OTP | — |
| RoHS 状态 | Non-compliant (legacy PDIP) | [DATA_NEEDED: RoHS compliance status] |
| Product Type | — | CMOS UV-Erasable Programmable Logic Device (EPLD) |
| Logic Macrocells | — | 16 |
| Dedicated Inputs | — | 4 |
| I/O Pins | — | 16 (bidirectional) |
| Total Usable Pins | — | 20 |
| Product Terms (p-terms) | — | 160 |
| Maximum Toggle Frequency (fMAX) | — | 55.6 MHz |
| Programming Method | — | UV erasure + parallel programmer |
| 安装类型 | — | Through-hole |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |