EP9100C-30 vs EP910DI-35 Vergleich

Detaillierter Direktvergleich von EP9100C-30 von Altera und EP910DI-35 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP9100C-30 EP910DI-35
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Aktiv
Lagerstatus In Stock In Stock
Stückpreis (USD) $7,95 $35,20
Family Altera Classic EPLD Altera Classic EPLD
Logic Density 900 usable gates (approx.) —
Macrocells 48 24
Flip-Flops 24 —
Dedicated Inputs 24 10
Propagation Delay (tPD) 30 ns 35 ns
Maximum Toggle Frequency (fMAX) 62.5 MHz —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) 4.75 V to 5.25 V (5 V nominal)
I/O Standard TTL-compatible —
Technology CMOS, UV-erasable (window) or OTP CMOS, UV-erasable EPROM
Betriebstemperatur 0C to +70C (commercial) -40C to +85C (industrial)
Gehäuse 40-pin ceramic DIP (CDIP) / 44-pin PLCC (windowed) / 40-pin PDIP CDIP-40 (Ceramic DIP with UV window)
Programming Method JEDEC via Altera APU or compatible programmer EPROM programmer + JEDEC fuse map
Montageart Through-Hole (DIP) / Surface Mount (PLCC) Through-Hole
RoHS-Status [DATA_NEEDED: rohs_status] [DATA_NEEDED: RoHS status - ceramic CDIP legacy parts are typically non-compliant unless specified]
Military Grade Variant EP9100C-30/883 (MIL-STD-883 compliant) —
Product Type — EPLD (Erasable Programmable Logic Device)
Usable Gates — 450
Maximum Toggle Frequency (fCNT) — 28.6 MHz
Supply Current (ICC) — 40 mA typical
Bidirectional I/O Pins — 20
Total Pins — 40
Erasure Method — UV light through quartz window
Logic Family — PAL-type AND/OR array with D flip-flops
Manufacturer — Original Altera; long-term authorized by Rochester Electronics, LLC

Datenblätter & Ressourcen

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