EP9100C-30 vs EP910DI-35 Comparison

Detailed side-by-side comparison of EP9100C-30 by Altera and EP910DI-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP9100C-30 EP910DI-35
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Active
Stock Status In Stock In Stock
Unit Price (USD) $7.95 $35.20
Family Altera Classic EPLD Altera Classic EPLD
Logic Density 900 usable gates (approx.) β€”
Macrocells 48 24
Flip-Flops 24 β€”
Dedicated Inputs 24 10
Propagation Delay (tPD) 30 ns 35 ns
Maximum Toggle Frequency (fMAX) 62.5 MHz β€”
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) 4.75 V to 5.25 V (5 V nominal)
I/O Standard TTL-compatible β€”
Technology CMOS, UV-erasable (window) or OTP CMOS, UV-erasable EPROM
Operating Temperature 0C to +70C (commercial) -40C to +85C (industrial)
Package 40-pin ceramic DIP (CDIP) / 44-pin PLCC (windowed) / 40-pin PDIP CDIP-40 (Ceramic DIP with UV window)
Programming Method JEDEC via Altera APU or compatible programmer EPROM programmer + JEDEC fuse map
Mounting Type Through-Hole (DIP) / Surface Mount (PLCC) Through-Hole
RoHS Status [DATA_NEEDED: rohs_status] [DATA_NEEDED: RoHS status - ceramic CDIP legacy parts are typically non-compliant unless specified]
Military Grade Variant EP9100C-30/883 (MIL-STD-883 compliant) β€”
Product Type β€” EPLD (Erasable Programmable Logic Device)
Usable Gates β€” 450
Maximum Toggle Frequency (fCNT) β€” 28.6 MHz
Supply Current (ICC) β€” 40 mA typical
Bidirectional I/O Pins β€” 20
Total Pins β€” 40
Erasure Method β€” UV light through quartz window
Logic Family β€” PAL-type AND/OR array with D flip-flops
Manufacturer β€” Original Altera; long-term authorized by Rochester Electronics, LLC

Datasheets & Resources

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