EP9100C-30 vs EP910DI-35 비교
다음의 상세 나란히 비교: EP9100C-30 제조: Altera 및 EP910DI-35 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP9100C-30 | EP910DI-35 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | 활성 |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $7.95 | $35.20 |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Logic Density | 900 usable gates (approx.) | — |
| Macrocells | 48 | 24 |
| Flip-Flops | 24 | — |
| Dedicated Inputs | 24 | 10 |
| Propagation Delay (tPD) | 30 ns | 35 ns |
| Maximum Toggle Frequency (fMAX) | 62.5 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 4.75 V to 5.25 V (5 V nominal) |
| I/O Standard | TTL-compatible | — |
| Technology | CMOS, UV-erasable (window) or OTP | CMOS, UV-erasable EPROM |
| 동작 온도 | 0C to +70C (commercial) | -40C to +85C (industrial) |
| 패키지 | 40-pin ceramic DIP (CDIP) / 44-pin PLCC (windowed) / 40-pin PDIP | CDIP-40 (Ceramic DIP with UV window) |
| Programming Method | JEDEC via Altera APU or compatible programmer | EPROM programmer + JEDEC fuse map |
| 실장 유형 | Through-Hole (DIP) / Surface Mount (PLCC) | Through-Hole |
| RoHS 상태 | [DATA_NEEDED: rohs_status] | [DATA_NEEDED: RoHS status - ceramic CDIP legacy parts are typically non-compliant unless specified] |
| Military Grade Variant | EP9100C-30/883 (MIL-STD-883 compliant) | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | — | 450 |
| Maximum Toggle Frequency (fCNT) | — | 28.6 MHz |
| Supply Current (ICC) | — | 40 mA typical |
| Bidirectional I/O Pins | — | 20 |
| Total Pins | — | 40 |
| Erasure Method | — | UV light through quartz window |
| Logic Family | — | PAL-type AND/OR array with D flip-flops |
| Manufacturer | — | Original Altera; long-term authorized by Rochester Electronics, LLC |