EP910DM-40 vs EP910ILC-25 Vergleich
Detaillierter Direktvergleich von EP910DM-40 von Altera und EP910ILC-25 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP910DM-40 | EP910ILC-25 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $21,00 | $9,95 |
| Product Type | UV Erasable Programmable Logic Device (EPLD) | — |
| Family | Altera Classic EP910 | EP910 Classic EPLD |
| Architecture | PAL-type AND/OR with global programmable interconnect bus | — |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 36 | — |
| Dedicated Outputs | 24 | — |
| Bidirectional I/O Lines | 24 | — |
| Product Terms | 240 | — |
| Propagation Delay (tPD) | 40 ns | 25 ns |
| External Clocks | 2 | — |
| Process Technology | CMOS | — |
| Gehäuse | 40-pin Ceramic DIP (Cerdip) with UV window | 44-pin JLCC (windowed ceramic) |
| Montageart | Through-Hole (DIP) | Surface Mount |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | -40C to +85C (industrial) |
| Versorgungsspannung | 5 V | 5 V |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | non_compliant (ceramic windowed package) |
| Programming Interface | JEDEC-standard fuse-map / UV erasure | — |
| User I/O Pins | — | 36 |
| Internal Frequency (fMAX) | — | [DATA_NEEDED: fMAX rating] |
| Logic Blocks | — | Sum-of-products AND/OR array |
| Technology | — | CMOS EPROM (UV-erasable) |
| Configuration Memory | — | Non-volatile EPROM (windowed ceramic) |
| Development Tool | — | Altera MAX+PLUS II (legacy) |
| Lebenszyklusstatus | — | Obsolete - last time buy was late 1990s |