EP910DM-40 vs EP910ILC-25 比較
詳細な並列比較: EP910DM-40 メーカー: Altera および EP910ILC-25 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP910DM-40 | EP910ILC-25 |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $21.00 | $9.95 |
| Product Type | UV Erasable Programmable Logic Device (EPLD) | — |
| Family | Altera Classic EP910 | EP910 Classic EPLD |
| Architecture | PAL-type AND/OR with global programmable interconnect bus | — |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 36 | — |
| Dedicated Outputs | 24 | — |
| Bidirectional I/O Lines | 24 | — |
| Product Terms | 240 | — |
| Propagation Delay (tPD) | 40 ns | 25 ns |
| External Clocks | 2 | — |
| Process Technology | CMOS | — |
| パッケージ | 40-pin Ceramic DIP (Cerdip) with UV window | 44-pin JLCC (windowed ceramic) |
| 実装タイプ | Through-Hole (DIP) | Surface Mount |
| 動作温度 | [DATA_NEEDED: operating temperature range] | -40C to +85C (industrial) |
| 電源電圧 | 5 V | 5 V |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance status] | non_compliant (ceramic windowed package) |
| Programming Interface | JEDEC-standard fuse-map / UV erasure | — |
| User I/O Pins | — | 36 |
| Internal Frequency (fMAX) | — | [DATA_NEEDED: fMAX rating] |
| Logic Blocks | — | Sum-of-products AND/OR array |
| Technology | — | CMOS EPROM (UV-erasable) |
| Configuration Memory | — | Non-volatile EPROM (windowed ceramic) |
| Development Tool | — | Altera MAX+PLUS II (legacy) |
| ライフサイクル状態 | — | Obsolete - last time buy was late 1990s |