EP910DM-40 vs EP910LC-35H Vergleich

Detaillierter Direktvergleich von EP910DM-40 von Altera und EP910LC-35H von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP910DM-40 EP910LC-35H
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $21,00 $25,00
Product Type UV Erasable Programmable Logic Device (EPLD) —
Family Altera Classic EP910 Classic EPLD (EP910)
Architecture PAL-type AND/OR with global programmable interconnect bus —
Macrocells 24 —
Dedicated Inputs 36 10
Dedicated Outputs 24 —
Bidirectional I/O Lines 24 —
Product Terms 240 —
Propagation Delay (tPD) 40 ns —
External Clocks 2 —
Process Technology CMOS —
Gehäuse 40-pin Ceramic DIP (Cerdip) with UV window 40-pin Ceramic DIP (H suffix)
Montageart Through-Hole (DIP) Through-hole (Ceramic DIP)
Betriebstemperatur [DATA_NEEDED: operating temperature range] [DATA_NEEDED: operating temperature range grade]
Versorgungsspannung 5 V —
RoHS-Status [DATA_NEEDED: RoHS compliance status] unknown
Programming Interface JEDEC-standard fuse-map / UV erasure —
Logic Elements — 24 macrocells
Equivalent Gates — 450 usable gates
Propagation Delay (tpd) — 35 ns
Supply Voltage (VCC) — 5 V (4.75 V to 5.25 V)
Technology — CMOS, UV-erasable EPROM
User I/O Pins — 36
Erasure Method — UV (quartz window on H package)
Programming Method — Altera hardware programmer
Logic Levels — TTL compatible
Ruhestrom — [DATA_NEEDED: typical ICC value]
Process Node — [DATA_NEEDED: process geometry]
Lifecycle — Obsolete (long-term supply via Rochester Electronics)

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