EP910DM883B vs EP910DC-40 Vergleich

Detaillierter Direktvergleich von EP910DM883B von Altera und EP910DC-40 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP910DM883B EP910DC-40
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $7,10 $13,95
Manufacturer Altera (now part of Intel) —
Family Classic EPLD - EP910 Series —
Device Type Erasable Programmable Logic Device (EPLD) —
Architecture PAL-type AND-OR-NOT, CMOS PAL-type AND/OR, UV-erasable CMOS
Macrocells 24 24
Inputs 36 —
Outputs 24 —
Product Terms 240 240 maximum
Propagation Delay (tPD) 40 ns (typical) —
Maximale Taktfrequenz 25 MHz —
Supply Voltage (VCC) 5 V —
Programming Voltage (VPP) 12.5 V (UV-erase window) —
Betriebstemperatur -55 °C to +125 °C (military) —
Gehäuse CDIP-40 (Ceramic DIP, 40-pin) DIP-40 (ceramic, through-hole)
Montageart Through-Hole (DIP) Through-Hole
MIL Processing MIL-STD-883B Class B —
Configuration Memory UV-erasable EPROM —
Logic Elements Combinational + Registered —
RoHS-Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: rohs_status]
Lead-Free [DATA_NEEDED: lead-free status] —
Device Family — Classic EPLD (EP910 series)
Dedicated Inputs — 12
Bidirectional I/O Pins — 24
Total Inputs to Logic Array — 36
Maximum Propagation Delay (tPD) — 40 ns
Maximum Operating Frequency (fMAX) — 25 MHz
Global Clocks — 2
Versorgungsspannung — 5 V (typical for Classic EPLD family)
Operating Temperature (Commercial) — 0 °C to 70 °C
Programming Method — UV-erase + EPROM programmer; on-board logic test circuitry

Datenblätter & Ressourcen

Alle Produkte durchsuchen BOM erstellen Angebot anfordern