EP910DM883B vs EP910DC-40 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP910DM883B disebabkan oleh Altera dan EP910DC-40 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EP910DM883B | EP910DC-40 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Manufacturer | Altera (now part of Intel) | — |
| Family | Classic EPLD - EP910 Series | — |
| Device Type | Erasable Programmable Logic Device (EPLD) | — |
| Architecture | PAL-type AND-OR-NOT, CMOS | PAL-type AND/OR, UV-erasable CMOS |
| Macrocells | 24 | 24 |
| Inputs | 36 | — |
| Outputs | 24 | — |
| Product Terms | 240 | 240 maximum |
| Propagation Delay (tPD) | 40 ns (typical) | — |
| Frekuensi Klock Maksimum | 25 MHz | — |
| Supply Voltage (VCC) | 5 V | — |
| Programming Voltage (VPP) | 12.5 V (UV-erase window) | — |
| Suhu Operasi | -55 °C to +125 °C (military) | — |
| Kemasan | CDIP-40 (Ceramic DIP, 40-pin) | DIP-40 (ceramic, through-hole) |
| Jenis Pemasangan | Through-Hole (DIP) | Through-Hole |
| MIL Processing | MIL-STD-883B Class B | — |
| Configuration Memory | UV-erasable EPROM | — |
| Logic Elements | Combinational + Registered | — |
| Status RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: rohs_status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Device Family | — | Classic EPLD (EP910 series) |
| Dedicated Inputs | — | 12 |
| Bidirectional I/O Pins | — | 24 |
| Total Inputs to Logic Array | — | 36 |
| Maximum Propagation Delay (tPD) | — | 40 ns |
| Maximum Operating Frequency (fMAX) | — | 25 MHz |
| Global Clocks | — | 2 |
| Tegangan Pemberi Arus | — | 5 V (typical for Classic EPLD family) |
| Operating Temperature (Commercial) | — | 0 °C to 70 °C |
| Programming Method | — | UV-erase + EPROM programmer; on-board logic test circuitry |