EP910DM883B vs EP910DI-35 Vergleich

Detaillierter Direktvergleich von EP910DM883B von Altera und EP910DI-35 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP910DM883B EP910DI-35
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Aktiv
Lagerstatus In Stock In Stock
Stückpreis (USD) $7,10 $35,20
Manufacturer Altera (now part of Intel) Original Altera; long-term authorized by Rochester Electronics, LLC
Family Classic EPLD - EP910 Series Altera Classic EPLD
Device Type Erasable Programmable Logic Device (EPLD) —
Architecture PAL-type AND-OR-NOT, CMOS —
Macrocells 24 24
Inputs 36 —
Outputs 24 —
Product Terms 240 —
Propagation Delay (tPD) 40 ns (typical) 35 ns
Maximale Taktfrequenz 25 MHz —
Supply Voltage (VCC) 5 V 4.75 V to 5.25 V (5 V nominal)
Programming Voltage (VPP) 12.5 V (UV-erase window) —
Betriebstemperatur -55 °C to +125 °C (military) -40C to +85C (industrial)
Gehäuse CDIP-40 (Ceramic DIP, 40-pin) CDIP-40 (Ceramic DIP with UV window)
Montageart Through-Hole (DIP) Through-Hole
MIL Processing MIL-STD-883B Class B —
Configuration Memory UV-erasable EPROM —
Logic Elements Combinational + Registered —
RoHS-Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status - ceramic CDIP legacy parts are typically non-compliant unless specified]
Lead-Free [DATA_NEEDED: lead-free status] —
Product Type — EPLD (Erasable Programmable Logic Device)
Usable Gates — 450
Maximum Toggle Frequency (fCNT) — 28.6 MHz
Supply Current (ICC) — 40 mA typical
Dedicated Inputs — 10
Bidirectional I/O Pins — 20
Total Pins — 40
Technology — CMOS, UV-erasable EPROM
Programming Method — EPROM programmer + JEDEC fuse map
Erasure Method — UV light through quartz window
Logic Family — PAL-type AND/OR array with D flip-flops

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