EP910DM883B vs EP910DI-35 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP910DM883B disebabkan oleh Altera dan EP910DI-35 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EP910DM883B | EP910DI-35 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Aktif |
| Manufacturer | Altera (now part of Intel) | Original Altera; long-term authorized by Rochester Electronics, LLC |
| Family | Classic EPLD - EP910 Series | Altera Classic EPLD |
| Device Type | Erasable Programmable Logic Device (EPLD) | — |
| Architecture | PAL-type AND-OR-NOT, CMOS | — |
| Macrocells | 24 | 24 |
| Inputs | 36 | — |
| Outputs | 24 | — |
| Product Terms | 240 | — |
| Propagation Delay (tPD) | 40 ns (typical) | 35 ns |
| Frekuensi Klock Maksimum | 25 MHz | — |
| Supply Voltage (VCC) | 5 V | 4.75 V to 5.25 V (5 V nominal) |
| Programming Voltage (VPP) | 12.5 V (UV-erase window) | — |
| Suhu Operasi | -55 °C to +125 °C (military) | -40C to +85C (industrial) |
| Kemasan | CDIP-40 (Ceramic DIP, 40-pin) | CDIP-40 (Ceramic DIP with UV window) |
| Jenis Pemasangan | Through-Hole (DIP) | Through-Hole |
| MIL Processing | MIL-STD-883B Class B | — |
| Configuration Memory | UV-erasable EPROM | — |
| Logic Elements | Combinational + Registered | — |
| Status RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status - ceramic CDIP legacy parts are typically non-compliant unless specified] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | — | 450 |
| Maximum Toggle Frequency (fCNT) | — | 28.6 MHz |
| Supply Current (ICC) | — | 40 mA typical |
| Dedicated Inputs | — | 10 |
| Bidirectional I/O Pins | — | 20 |
| Total Pins | — | 40 |
| Technology | — | CMOS, UV-erasable EPROM |
| Programming Method | — | EPROM programmer + JEDEC fuse map |
| Erasure Method | — | UV light through quartz window |
| Logic Family | — | PAL-type AND/OR array with D flip-flops |