EP910IDI-15 vs EP910DC-15 Vergleich

Detaillierter Direktvergleich von EP910IDI-15 von Altera und EP910DC-15 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP910IDI-15 EP910DC-15
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $29,00 $10,75
Family Classic EPLD Altera Classic EPLD
Device Type CPLD (Complex Programmable Logic Device) —
Logic Gates 450 gates —
Macrocells 24 24
Maximum User I/O Pins 36 —
Pin-to-Pin Propagation Delay (tpd) 15 ns —
Maximum Counter Frequency 66.6 MHz —
Supply Voltage (Vcc) 5 V —
Technology CMOS EPROM CMOS EPROM, UV-erasable
Program/Erase Method UV-erasable windowed CerDIP —
Gehäuse 40-pin CDIP (CerDIP) with quartz window 24-pin ceramic DIP (DC)
Betriebstemperatur -40C to +85C (industrial, "I" grade) 0C to +70C (commercial)
Montageart Through-hole (DIP) Through-Hole
Macrocells Configurable As D, T, JK, SR flip-flop, or combinatorial —
Development Tool MAX+PLUS II (legacy) / Altera Classic compiler —
Programming Hardware Altera Logic Programmer card —
RoHS-Status [DATA_NEEDED: RoHS compliance of CDIP windowed part] [DATA_NEEDED: not explicitly stated in verified data]
Logic Family Compatibility Pin-, function-, and JEDEC-map compatible across all EP910 speed grades and packages —
Device Density — 900 usable gates
Logic Elements — [DATA_NEEDED: exact LE count]
Dedicated Inputs — 12
Bidirectional I/O Pins — 12
Flip-Flops — 10
Product Terms per Macrocells — 24
Maximum Propagation Delay (tPD) — 15 ns
Speed Grade — 15
Supply Voltage (VCC) — 5 V (typical)
MSL-Level — [DATA_NEEDED: MSL level]

Datenblätter & Ressourcen

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