EP910IDI-15 vs EP910DC-15 对比
详细并排对比 EP910IDI-15 出自 Altera 和 EP910DC-15 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP910IDI-15 | EP910DC-15 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $29.00 | $10.75 |
| Family | Classic EPLD | Altera Classic EPLD |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Logic Gates | 450 gates | — |
| Macrocells | 24 | 24 |
| Maximum User I/O Pins | 36 | — |
| Pin-to-Pin Propagation Delay (tpd) | 15 ns | — |
| Maximum Counter Frequency | 66.6 MHz | — |
| Supply Voltage (Vcc) | 5 V | — |
| Technology | CMOS EPROM | CMOS EPROM, UV-erasable |
| Program/Erase Method | UV-erasable windowed CerDIP | — |
| 封装 | 40-pin CDIP (CerDIP) with quartz window | 24-pin ceramic DIP (DC) |
| 工作温度 | -40C to +85C (industrial, "I" grade) | 0C to +70C (commercial) |
| 安装类型 | Through-hole (DIP) | Through-Hole |
| Macrocells Configurable As | D, T, JK, SR flip-flop, or combinatorial | — |
| Development Tool | MAX+PLUS II (legacy) / Altera Classic compiler | — |
| Programming Hardware | Altera Logic Programmer card | — |
| RoHS 状态 | [DATA_NEEDED: RoHS compliance of CDIP windowed part] | [DATA_NEEDED: not explicitly stated in verified data] |
| Logic Family Compatibility | Pin-, function-, and JEDEC-map compatible across all EP910 speed grades and packages | — |
| Device Density | — | 900 usable gates |
| Logic Elements | — | [DATA_NEEDED: exact LE count] |
| Dedicated Inputs | — | 12 |
| Bidirectional I/O Pins | — | 12 |
| Flip-Flops | — | 10 |
| Product Terms per Macrocells | — | 24 |
| Maximum Propagation Delay (tPD) | — | 15 ns |
| Speed Grade | — | 15 |
| Supply Voltage (VCC) | — | 5 V (typical) |
| MSL 等级 | — | [DATA_NEEDED: MSL level] |