EP910ILC-25 vs EP910ILC-50 Vergleich
Detaillierter Direktvergleich von EP910ILC-25 von Intel und EP910ILC-50 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP910ILC-25 | EP910ILC-50 |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,95 | $10,85 |
| Family | EP910 Classic EPLD | Altera Classic EPLD |
| Macrocells | 24 | 24 |
| User I/O Pins | 36 | 24 |
| Propagation Delay (tPD) | 25 ns | — |
| Internal Frequency (fMAX) | [DATA_NEEDED: fMAX rating] | — |
| Logic Blocks | Sum-of-products AND/OR array | — |
| Technology | CMOS EPROM (UV-erasable) | CMOS EPROM, UV-erasable |
| Configuration Memory | Non-volatile EPROM (windowed ceramic) | — |
| Gehäuse | 44-pin JLCC (windowed ceramic) | PLCC-44 (J-lead) |
| Montageart | Surface Mount | Surface Mount (socket-compatible) |
| Betriebstemperatur | -40C to +85C (industrial) | 0C to +70C (commercial) |
| Versorgungsspannung | 5 V | — |
| Development Tool | Altera MAX+PLUS II (legacy) | — |
| RoHS-Status | non_compliant (ceramic windowed package) | [DATA_NEEDED: RoHS compliance status] |
| Lebenszyklusstatus | Obsolete - last time buy was late 1990s | — |
| Usable Gates | — | 900 (typical) |
| Maximum Frequency | — | [DATA_NEEDED: fMAX value from datasheet] |
| Pin-to-Pin Delay (tpd) | — | 50 ns |
| Supply Voltage (VCC) | — | 5 V (typical) |
| Dedicated Input Pins | — | 12 |
| Programming Cycles | — | 100 (minimum) |
| Boundary Scan | — | IEEE 1149.1 JTAG (selected speed grades) |