EP910ILC-25 vs EP910ILC-50 比較
詳細な並列比較: EP910ILC-25 メーカー: Intel および EP910ILC-50 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP910ILC-25 | EP910ILC-50 |
|---|---|---|
| ブランド | Intel | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $9.95 | $10.85 |
| Family | EP910 Classic EPLD | Altera Classic EPLD |
| Macrocells | 24 | 24 |
| User I/O Pins | 36 | 24 |
| Propagation Delay (tPD) | 25 ns | — |
| Internal Frequency (fMAX) | [DATA_NEEDED: fMAX rating] | — |
| Logic Blocks | Sum-of-products AND/OR array | — |
| Technology | CMOS EPROM (UV-erasable) | CMOS EPROM, UV-erasable |
| Configuration Memory | Non-volatile EPROM (windowed ceramic) | — |
| パッケージ | 44-pin JLCC (windowed ceramic) | PLCC-44 (J-lead) |
| 実装タイプ | Surface Mount | Surface Mount (socket-compatible) |
| 動作温度 | -40C to +85C (industrial) | 0C to +70C (commercial) |
| 電源電圧 | 5 V | — |
| Development Tool | Altera MAX+PLUS II (legacy) | — |
| RoHS ステータス | non_compliant (ceramic windowed package) | [DATA_NEEDED: RoHS compliance status] |
| ライフサイクル状態 | Obsolete - last time buy was late 1990s | — |
| Usable Gates | — | 900 (typical) |
| Maximum Frequency | — | [DATA_NEEDED: fMAX value from datasheet] |
| Pin-to-Pin Delay (tpd) | — | 50 ns |
| Supply Voltage (VCC) | — | 5 V (typical) |
| Dedicated Input Pins | — | 12 |
| Programming Cycles | — | 100 (minimum) |
| Boundary Scan | — | IEEE 1149.1 JTAG (selected speed grades) |