EP910ILC-25 vs EP910ILC-50 对比
详细并排对比 EP910ILC-25 出自 Intel 和 EP910ILC-50 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP910ILC-25 | EP910ILC-50 |
|---|---|---|
| 品牌 | Intel | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $9.95 | $10.85 |
| Family | EP910 Classic EPLD | Altera Classic EPLD |
| Macrocells | 24 | 24 |
| User I/O Pins | 36 | 24 |
| Propagation Delay (tPD) | 25 ns | — |
| Internal Frequency (fMAX) | [DATA_NEEDED: fMAX rating] | — |
| Logic Blocks | Sum-of-products AND/OR array | — |
| Technology | CMOS EPROM (UV-erasable) | CMOS EPROM, UV-erasable |
| Configuration Memory | Non-volatile EPROM (windowed ceramic) | — |
| 封装 | 44-pin JLCC (windowed ceramic) | PLCC-44 (J-lead) |
| 安装类型 | Surface Mount | Surface Mount (socket-compatible) |
| 工作温度 | -40C to +85C (industrial) | 0C to +70C (commercial) |
| 电源电压 | 5 V | — |
| Development Tool | Altera MAX+PLUS II (legacy) | — |
| RoHS 状态 | non_compliant (ceramic windowed package) | [DATA_NEEDED: RoHS compliance status] |
| 生命周期状态 | Obsolete - last time buy was late 1990s | — |
| Usable Gates | — | 900 (typical) |
| Maximum Frequency | — | [DATA_NEEDED: fMAX value from datasheet] |
| Pin-to-Pin Delay (tpd) | — | 50 ns |
| Supply Voltage (VCC) | — | 5 V (typical) |
| Dedicated Input Pins | — | 12 |
| Programming Cycles | — | 100 (minimum) |
| Boundary Scan | — | IEEE 1149.1 JTAG (selected speed grades) |