EP910IPC-15 vs EP910DC-35 Vergleich
Detaillierter Direktvergleich von EP910IPC-15 von Altera und EP910DC-35 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP910IPC-15 | EP910DC-35 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $7,95 | $10,95 |
| Device Family | Altera Classic EPLD (EP910 series) | — |
| Product Type | Erasable Programmable Logic Device (EPLD) | — |
| Architecture | PAL-type, CMOS | PAL-type sum-of-products AND-OR array |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 12 |
| I/O Pins | 24 | 24 |
| Product Terms | 240 | 240 |
| External Clocks | 2 | — |
| Propagation Delay (tPD) | 15 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Betriebstemperatur | 0C to +70C (commercial, IPC suffix) | 0 °C to +70 °C (commercial) |
| Gehäuse | PDIP-40 (Plastic DIP, 40-pin) | 40-pin CDIP (Ceramic DIP) with quartz window |
| Montageart | Through-Hole | — |
| Process Technology | CMOS | — |
| Programming Method | JEDEC fuse map via Altera EPLD programmer | JEDEC fuse map via device programmer; UV erase |
| Pin-Anzahl | 40 | — |
| RoHS-Status | [DATA_NEEDED: rohs status not confirmed in verified data] | Non-compliant (ceramic DIP with Pb-bearing lead finish) |
| Device Type | — | UV-Erasable CMOS PLD (PAL-type) |
| Family | — | Classic EPLD EP910 |
| Usable Gates | — | 900 gates |
| Total Inputs | — | 36 |
| Propagation Delay (tpd) | — | 35 ns |
| Maximale Taktfrequenz | — | 37 MHz (typical, internal) |
| Supply Voltage (Vcc) | — | 4.75 V to 5.25 V (5 V nominal) |
| Lead Pitch | — | 2.540 mm |
| Termination Style | — | Through-Hole |
| Technology | — | CMOS, UV-erasable EPROM cell |
| Lifecycle | — | Obsolete / last-time-buy from authorized distributors |