EP910IPC-15 vs EP910IPC-25 Vergleich
Detaillierter Direktvergleich von EP910IPC-15 von Altera und EP910IPC-25 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP910IPC-15 | EP910IPC-25 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $7,95 | $10,40 |
| Device Family | Altera Classic EPLD (EP910 series) | — |
| Product Type | Erasable Programmable Logic Device (EPLD) | — |
| Architecture | PAL-type, CMOS | PAL-type EPLD, CMOS, UV/OTP |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 12 |
| I/O Pins | 24 | — |
| Product Terms | 240 | 240 |
| External Clocks | 2 | — |
| Propagation Delay (tPD) | 15 ns | 25 ns |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V |
| Betriebstemperatur | 0C to +70C (commercial, IPC suffix) | 0C to +70C (commercial grade) |
| Gehäuse | PDIP-40 (Plastic DIP, 40-pin) | 40-pin PDIP (PDIP-40) |
| Montageart | Through-Hole | Through-Hole |
| Process Technology | CMOS | — |
| Programming Method | JEDEC fuse map via Altera EPLD programmer | EPROM cell (OTP / UV erasable) |
| Pin-Anzahl | 40 | — |
| RoHS-Status | [DATA_NEEDED: rohs status not confirmed in verified data] | — |
| Family | — | Classic EPLD (EP910 series) |
| Manufacturer | — | Altera (now Intel) |
| Usable Gates | — | 450 |
| Maximum Frequency (fMAX) | — | 40 MHz |
| Bidirectional I/O Lines | — | 24 |
| Total Inputs (max) | — | 36 |
| Total Outputs (max) | — | 24 |
| Development Tool | — | MAX+PLUS II |