EP910IPC-15 vs EP910IPC-25 比較
詳細な並列比較: EP910IPC-15 メーカー: Altera および EP910IPC-25 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP910IPC-15 | EP910IPC-25 |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $7.95 | $10.40 |
| Device Family | Altera Classic EPLD (EP910 series) | — |
| Product Type | Erasable Programmable Logic Device (EPLD) | — |
| Architecture | PAL-type, CMOS | PAL-type EPLD, CMOS, UV/OTP |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 12 |
| I/O Pins | 24 | — |
| Product Terms | 240 | 240 |
| External Clocks | 2 | — |
| Propagation Delay (tPD) | 15 ns | 25 ns |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V |
| 動作温度 | 0C to +70C (commercial, IPC suffix) | 0C to +70C (commercial grade) |
| パッケージ | PDIP-40 (Plastic DIP, 40-pin) | 40-pin PDIP (PDIP-40) |
| 実装タイプ | Through-Hole | Through-Hole |
| Process Technology | CMOS | — |
| Programming Method | JEDEC fuse map via Altera EPLD programmer | EPROM cell (OTP / UV erasable) |
| ピン数 | 40 | — |
| RoHS ステータス | [DATA_NEEDED: rohs status not confirmed in verified data] | — |
| Family | — | Classic EPLD (EP910 series) |
| Manufacturer | — | Altera (now Intel) |
| Usable Gates | — | 450 |
| Maximum Frequency (fMAX) | — | 40 MHz |
| Bidirectional I/O Lines | — | 24 |
| Total Inputs (max) | — | 36 |
| Total Outputs (max) | — | 24 |
| Development Tool | — | MAX+PLUS II |