EP910LC-35H vs EP910LC-35T Vergleich
Detaillierter Direktvergleich von EP910LC-35H von Altera und EP910LC-35T von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP910LC-35H | EP910LC-35T |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $25,00 | $28,90 |
| Family | Classic EPLD (EP910) | Classic EPLD (EP910) |
| Logic Elements | 24 macrocells | — |
| Equivalent Gates | 450 usable gates | — |
| Propagation Delay (tpd) | 35 ns | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | 5 V |
| Technology | CMOS, UV-erasable EPROM | — |
| Gehäuse | 40-pin Ceramic DIP (H suffix) | PLCC-44 (J-lead) |
| User I/O Pins | 36 | 36 |
| Dedicated Inputs | 10 | — |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range grade] | 0C to +70C (commercial) |
| Erasure Method | UV (quartz window on H package) | UV-erasable window (ceramic package) / OTP (plastic) |
| Programming Method | Altera hardware programmer | — |
| Logic Levels | TTL compatible | — |
| Ruhestrom | [DATA_NEEDED: typical ICC value] | — |
| Process Node | [DATA_NEEDED: process geometry] | — |
| Montageart | Through-hole (Ceramic DIP) | Surface Mount (PLCC socket or solder) |
| RoHS-Status | unknown | [DATA_NEEDED: RoHS status not in verified data] |
| Lifecycle | Obsolete (long-term supply via Rochester Electronics) | — |
| Logic Capacity | — | 450 usable gates |
| Macrocells | — | 24 |
| Propagation Delay (tPD) | — | 35 ns |
| Maximum Operating Frequency | — | 28.6 MHz |
| Process Technology | — | CMOS (EPROM-based) |
| Programming | — | Altera programming hardware + MAX+PLUS II |
| MSL-Level | — | MSL 3 (168 hours) |