EP910LC-35H vs EP910LC-35T Comparaison
Comparaison détaillée côte à côte de EP910LC-35H par Altera et EP910LC-35T par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP910LC-35H | EP910LC-35T |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $25,00 | $28,90 |
| Family | Classic EPLD (EP910) | Classic EPLD (EP910) |
| Logic Elements | 24 macrocells | — |
| Equivalent Gates | 450 usable gates | — |
| Propagation Delay (tpd) | 35 ns | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | 5 V |
| Technology | CMOS, UV-erasable EPROM | — |
| Boîtier | 40-pin Ceramic DIP (H suffix) | PLCC-44 (J-lead) |
| User I/O Pins | 36 | 36 |
| Dedicated Inputs | 10 | — |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range grade] | 0C to +70C (commercial) |
| Erasure Method | UV (quartz window on H package) | UV-erasable window (ceramic package) / OTP (plastic) |
| Programming Method | Altera hardware programmer | — |
| Logic Levels | TTL compatible | — |
| Courant de repos | [DATA_NEEDED: typical ICC value] | — |
| Process Node | [DATA_NEEDED: process geometry] | — |
| Type de montage | Through-hole (Ceramic DIP) | Surface Mount (PLCC socket or solder) |
| Statut RoHS | unknown | [DATA_NEEDED: RoHS status not in verified data] |
| Lifecycle | Obsolete (long-term supply via Rochester Electronics) | — |
| Logic Capacity | — | 450 usable gates |
| Macrocells | — | 24 |
| Propagation Delay (tPD) | — | 35 ns |
| Maximum Operating Frequency | — | 28.6 MHz |
| Process Technology | — | CMOS (EPROM-based) |
| Programming | — | Altera programming hardware + MAX+PLUS II |
| Niveau MSL | — | MSL 3 (168 hours) |