EP910PC-20T vs EP910PC-0 Vergleich
Detaillierter Direktvergleich von EP910PC-20T von Altera und EP910PC-0 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP910PC-20T | EP910PC-0 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Unknown | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $8,70 | $8,70 |
| Device Type | EPLD | — |
| Family | Classic EPLD | Classic EPLD |
| Fabrication Technology | CMOS | — |
| Logic Integration | 300 to 900 usable gates | — |
| Logic Emulation | 100% TTL emulation | — |
| Application Function | High-speed, low-power logic integration | — |
| Programmable Device Class | Erasable programmable logic device | — |
| Device Family | Altera Classic EPLD Family | — |
| Speed Grade | 20 ns | -0 (slowest) |
| Package Code | PC | — |
| Package Pin Count | [DATA_NEEDED: package pin count] | — |
| Package Dimensions | [DATA_NEEDED: package dimensions] | — |
| Versorgungsspannung | [DATA_NEEDED: operating supply voltage] | 5 V (single supply) |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| I/O Count | [DATA_NEEDED: I/O count] | — |
| Internal Logic Capacity | 300 to 900 usable gates | — |
| Supported Logic Integration | Multiple PAL- and GAL-type devices | — |
| Programming Interface | [DATA_NEEDED: programming interface] | — |
| Programming Voltage | [DATA_NEEDED: programming voltage] | — |
| Mounting Technology | [DATA_NEEDED: mounting technology] | — |
| RoHS-Status | unknown | — |
| REACH Status | unknown | — |
| AEC-Q100 Qualification | not_applicable | — |
| Lead-Free Status | unknown | — |
| Halogen-Free Status | unknown | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | — | 900 gates |
| Macrocells | — | 24 |
| Logic Blocks | — | 6 (4 macrocells each) |
| Dedicated Inputs | — | 10 |
| I/O Pins | — | 24 |
| Gehäuse | — | PDIP-40 (Plastic DIP, 40-pin) |
| Process Technology | — | CMOS |
| Logic Compatibility | — | 100% TTL emulation |
| Programming Method | — | UV-erasable / OTP |
| Montageart | — | Through-Hole (DIP) |