EP910PC-20T vs EP910PC-0 Comparaison
Comparaison détaillée côte à côte de EP910PC-20T par Altera et EP910PC-0 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP910PC-20T | EP910PC-0 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Unknown | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $8,70 | $8,70 |
| Device Type | EPLD | — |
| Family | Classic EPLD | Classic EPLD |
| Fabrication Technology | CMOS | — |
| Logic Integration | 300 to 900 usable gates | — |
| Logic Emulation | 100% TTL emulation | — |
| Application Function | High-speed, low-power logic integration | — |
| Programmable Device Class | Erasable programmable logic device | — |
| Device Family | Altera Classic EPLD Family | — |
| Speed Grade | 20 ns | -0 (slowest) |
| Package Code | PC | — |
| Package Pin Count | [DATA_NEEDED: package pin count] | — |
| Package Dimensions | [DATA_NEEDED: package dimensions] | — |
| Tension d'alimentation | [DATA_NEEDED: operating supply voltage] | 5 V (single supply) |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| I/O Count | [DATA_NEEDED: I/O count] | — |
| Internal Logic Capacity | 300 to 900 usable gates | — |
| Supported Logic Integration | Multiple PAL- and GAL-type devices | — |
| Programming Interface | [DATA_NEEDED: programming interface] | — |
| Programming Voltage | [DATA_NEEDED: programming voltage] | — |
| Mounting Technology | [DATA_NEEDED: mounting technology] | — |
| Statut RoHS | unknown | — |
| REACH Status | unknown | — |
| AEC-Q100 Qualification | not_applicable | — |
| Lead-Free Status | unknown | — |
| Halogen-Free Status | unknown | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | — | 900 gates |
| Macrocells | — | 24 |
| Logic Blocks | — | 6 (4 macrocells each) |
| Dedicated Inputs | — | 10 |
| I/O Pins | — | 24 |
| Boîtier | — | PDIP-40 (Plastic DIP, 40-pin) |
| Process Technology | — | CMOS |
| Logic Compatibility | — | 100% TTL emulation |
| Programming Method | — | UV-erasable / OTP |
| Type de montage | — | Through-Hole (DIP) |