EP910PC-20T vs EP910PC-0 비교

다음의 상세 나란히 비교: EP910PC-20T 제조: Altera 및 EP910PC-0 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

사양 비교

파라미터 EP910PC-20T EP910PC-0
브랜드 Altera Altera
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 Unknown Obsolete
재고 상태 In Stock In Stock
단가 (USD) $8.70 $8.70
Device Type EPLD —
Family Classic EPLD Classic EPLD
Fabrication Technology CMOS —
Logic Integration 300 to 900 usable gates —
Logic Emulation 100% TTL emulation —
Application Function High-speed, low-power logic integration —
Programmable Device Class Erasable programmable logic device —
Device Family Altera Classic EPLD Family —
Speed Grade 20 ns -0 (slowest)
Package Code PC —
Package Pin Count [DATA_NEEDED: package pin count] —
Package Dimensions [DATA_NEEDED: package dimensions] —
공급 전압 [DATA_NEEDED: operating supply voltage] 5 V (single supply)
동작 온도 [DATA_NEEDED: operating temperature range] 0C to +70C (commercial)
I/O Count [DATA_NEEDED: I/O count] —
Internal Logic Capacity 300 to 900 usable gates —
Supported Logic Integration Multiple PAL- and GAL-type devices —
Programming Interface [DATA_NEEDED: programming interface] —
Programming Voltage [DATA_NEEDED: programming voltage] —
Mounting Technology [DATA_NEEDED: mounting technology] —
RoHS 상태 unknown —
REACH Status unknown —
AEC-Q100 Qualification not_applicable —
Lead-Free Status unknown —
Halogen-Free Status unknown —
Product Type — EPLD (Erasable Programmable Logic Device)
Usable Gates — 900 gates
Macrocells — 24
Logic Blocks — 6 (4 macrocells each)
Dedicated Inputs — 10
I/O Pins — 24
패키지 — PDIP-40 (Plastic DIP, 40-pin)
Process Technology — CMOS
Logic Compatibility — 100% TTL emulation
Programming Method — UV-erasable / OTP
실장 유형 — Through-Hole (DIP)

데이터시트 & 자료

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