EP910PC-30 vs EP910PC30T Vergleich
Detaillierter Direktvergleich von EP910PC-30 von Altera und EP910PC30T von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EP910PC-30 | EP910PC30T |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $6,50 | $8,85 |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Macrocells | 24 | — |
| Usable Gates | ~450 | — |
| Pin-to-Pin Propagation Delay (tPD) | 30 ns | — |
| Maximum Counter Frequency (fCNT) | 33.3 MHz | — |
| Supply Voltage (VCC) | 5 V ±10% | 5 V (4.75 V to 5.25 V) |
| Logic Inputs | 36 dedicated | — |
| I/O Pins | 12 bidirectional | — |
| Logic Array Blocks (LABs) | 4 | — |
| Gehäuse | PDIP-40 (plastic DIP, 0.6 inch) | 24-pin PDIP (PC) |
| Betriebstemperatur | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| Programming Technology | UV-erasable EPROM cell | EPROM (OTP in plastic package, UV-erasable in windowed package) |
| TTL Emulation | 100% TTL-compatible | — |
| Power Dissipation | [DATA_NEEDED: power dissipation mW] | — |
| RoHS-Status | Non-compliant (contains lead, PDIP package) | [DATA_NEEDED: RoHS compliance status] |
| Montageart | Through-hole DIP | Through-Hole (THT) |
| Device Series | — | EP910 |
| Number of Macrocells | — | 24 |
| Number of I/O Pins | — | 24 |
| Number of Dedicated Inputs | — | 12 |
| Maximum Product Terms | — | 240 |
| Propagation Delay (tPD) | — | 30 ns |
| Maximum Clock Frequency (fMAX) | — | 33.3 MHz |
| Process Technology | — | CMOS |
| Programmable Logic Architecture | — | PAL-type sum-of-products, EPLD |
| Speed Grade | — | -30 (30 ns tPD) |
| Pin-Anzahl | — | 24 |