EP910PC-30 vs EP910PC30T 比較
詳細な並列比較: EP910PC-30 メーカー: Altera および EP910PC30T メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP910PC-30 | EP910PC30T |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $6.50 | $8.85 |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Macrocells | 24 | — |
| Usable Gates | ~450 | — |
| Pin-to-Pin Propagation Delay (tPD) | 30 ns | — |
| Maximum Counter Frequency (fCNT) | 33.3 MHz | — |
| Supply Voltage (VCC) | 5 V ±10% | 5 V (4.75 V to 5.25 V) |
| Logic Inputs | 36 dedicated | — |
| I/O Pins | 12 bidirectional | — |
| Logic Array Blocks (LABs) | 4 | — |
| パッケージ | PDIP-40 (plastic DIP, 0.6 inch) | 24-pin PDIP (PC) |
| 動作温度 | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| Programming Technology | UV-erasable EPROM cell | EPROM (OTP in plastic package, UV-erasable in windowed package) |
| TTL Emulation | 100% TTL-compatible | — |
| Power Dissipation | [DATA_NEEDED: power dissipation mW] | — |
| RoHS ステータス | Non-compliant (contains lead, PDIP package) | [DATA_NEEDED: RoHS compliance status] |
| 実装タイプ | Through-hole DIP | Through-Hole (THT) |
| Device Series | — | EP910 |
| Number of Macrocells | — | 24 |
| Number of I/O Pins | — | 24 |
| Number of Dedicated Inputs | — | 12 |
| Maximum Product Terms | — | 240 |
| Propagation Delay (tPD) | — | 30 ns |
| Maximum Clock Frequency (fMAX) | — | 33.3 MHz |
| Process Technology | — | CMOS |
| Programmable Logic Architecture | — | PAL-type sum-of-products, EPLD |
| Speed Grade | — | -30 (30 ns tPD) |
| ピン数 | — | 24 |