EP910PC-30 vs EP910PC30T Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910PC-30 sa pamamagitan ng Altera at EP910PC30T sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910PC-30 | EP910PC30T |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Macrocells | 24 | — |
| Usable Gates | ~450 | — |
| Pin-to-Pin Propagation Delay (tPD) | 30 ns | — |
| Maximum Counter Frequency (fCNT) | 33.3 MHz | — |
| Supply Voltage (VCC) | 5 V ±10% | 5 V (4.75 V to 5.25 V) |
| Logic Inputs | 36 dedicated | — |
| I/O Pins | 12 bidirectional | — |
| Logic Array Blocks (LABs) | 4 | — |
| Packhaging | PDIP-40 (plastic DIP, 0.6 inch) | 24-pin PDIP (PC) |
| Temperature na Operasyon | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| Programming Technology | UV-erasable EPROM cell | EPROM (OTP in plastic package, UV-erasable in windowed package) |
| TTL Emulation | 100% TTL-compatible | — |
| Power Dissipation | [DATA_NEEDED: power dissipation mW] | — |
| Tindminan RoHS | Non-compliant (contains lead, PDIP package) | [DATA_NEEDED: RoHS compliance status] |
| Uri ng Pagpapasok | Through-hole DIP | Through-Hole (THT) |
| Device Series | — | EP910 |
| Number of Macrocells | — | 24 |
| Number of I/O Pins | — | 24 |
| Number of Dedicated Inputs | — | 12 |
| Maximum Product Terms | — | 240 |
| Propagation Delay (tPD) | — | 30 ns |
| Maximum Clock Frequency (fMAX) | — | 33.3 MHz |
| Process Technology | — | CMOS |
| Programmable Logic Architecture | — | PAL-type sum-of-products, EPLD |
| Speed Grade | — | -30 (30 ns tPD) |
| Bilang ng Pin | — | 24 |