EP910PI-20 vs EP910PI-15T Vergleich

Detaillierter Direktvergleich von EP910PI-20 von Altera und EP910PI-15T von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EP910PI-20 EP910PI-15T
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $9,75 $10,95
Device Family Altera Classic EPLD Family —
Macrocells 24 24
Propagation Delay (tPD) 20 ns 15 ns max (speed grade -15)
Gehäuse PDIP-40 (PI suffix) 40-pin PDIP (Plastic DIP, R-PDIP-T40)
Montageart Through-Hole Through-Hole
Supply Voltage (VCC) 5 V (+/- 5%) —
Betriebstemperatur -40C to +85C (industrial) [DATA_NEEDED: industrial/commercial temp range]
Technology CMOS EPROM (UV-erasable windowed variants available) CMOS EEPROM (electrically erasable)
Configuration Method Non-volatile EPROM (no boot PROM required) —
Dedicated Inputs 12 12
Bidirectional I/O Pins 24 —
Maximum Counter Frequency 125 MHz —
Output Drive Current (IOL) 24 mA (TTL-compatible) —
Programmable Polarity Yes (XOR gate per macrocell) —
Macrocell Flip-Flop Yes (D-type, programmable) —
Power Dissipation [DATA_NEEDED: typical power dissipation in mW] —
Programming Interface JEDEC file via Altera programming hardware —
RoHS-Status unknown [DATA_NEEDED: original Altera part; likely non-RoHS as 5V PDIP]
MIL-STD-883 Variant EP910DM/883B (separate part number) —
Product Type — Classic EPLD (Erasable Programmable Logic Device)
Family — Altera Classic EPLD (EP910 series)
I/O Pins — 24
Logic Blocks — 6 LABs of 4 macrocells each (Classic architecture)
Versorgungsspannung — 4.5 V to 5.5 V (5 V nominal)
Output Drive Current — [DATA_NEEDED: per-pin DC output current, mA]
Programming — JEDEC-standard, serial/parallel programmer

Datenblätter & Ressourcen

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