EP910PI-20 vs EP910PI-15T 비교
다음의 상세 나란히 비교: EP910PI-20 제조: Altera 및 EP910PI-15T 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP910PI-20 | EP910PI-15T |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $9.75 | $10.95 |
| Device Family | Altera Classic EPLD Family | — |
| Macrocells | 24 | 24 |
| Propagation Delay (tPD) | 20 ns | 15 ns max (speed grade -15) |
| 패키지 | PDIP-40 (PI suffix) | 40-pin PDIP (Plastic DIP, R-PDIP-T40) |
| 실장 유형 | Through-Hole | Through-Hole |
| Supply Voltage (VCC) | 5 V (+/- 5%) | — |
| 동작 온도 | -40C to +85C (industrial) | [DATA_NEEDED: industrial/commercial temp range] |
| Technology | CMOS EPROM (UV-erasable windowed variants available) | CMOS EEPROM (electrically erasable) |
| Configuration Method | Non-volatile EPROM (no boot PROM required) | — |
| Dedicated Inputs | 12 | 12 |
| Bidirectional I/O Pins | 24 | — |
| Maximum Counter Frequency | 125 MHz | — |
| Output Drive Current (IOL) | 24 mA (TTL-compatible) | — |
| Programmable Polarity | Yes (XOR gate per macrocell) | — |
| Macrocell Flip-Flop | Yes (D-type, programmable) | — |
| Power Dissipation | [DATA_NEEDED: typical power dissipation in mW] | — |
| Programming Interface | JEDEC file via Altera programming hardware | — |
| RoHS 상태 | unknown | [DATA_NEEDED: original Altera part; likely non-RoHS as 5V PDIP] |
| MIL-STD-883 Variant | EP910DM/883B (separate part number) | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Family | — | Altera Classic EPLD (EP910 series) |
| I/O Pins | — | 24 |
| Logic Blocks | — | 6 LABs of 4 macrocells each (Classic architecture) |
| 공급 전압 | — | 4.5 V to 5.5 V (5 V nominal) |
| Output Drive Current | — | [DATA_NEEDED: per-pin DC output current, mA] |
| Programming | — | JEDEC-standard, serial/parallel programmer |