EP910PI-40 vs EP910PI-30T Vergleich

Detaillierter Direktvergleich von EP910PI-40 von Altera und EP910PI-30T von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Altera
EP910PI-40 EP910PI-40 - 24-Macrocell Classic EPLD, 43ns, PDIP-40 | Altera

EP910PI-40 - 24-Macrocell Classic EPLD, 43ns, PDIP-40 | Altera

EP910PI-40 ⚠ Letzte Bestellmöglichkeit

Spezifikationsvergleich

Parameter EP910PI-40 EP910PI-30T
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Letzte Kaufgelegenheit Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $9,85 $10,95
Device Family Classic EPLD —
Part Number EP910PI-40 —
Architecture PAL-type macrocell, CMOS, UV-erasable —
Number of Macrocells 24 —
Number of Dedicated Inputs 12 —
Number of I/O Lines 24 —
External Clock Inputs 2 —
Maximale Taktfrequenz 25 MHz —
Propagation Delay (tPD) 43 ns 30 ns
Speed Grade -40 (43 ns) —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) 4.75 V to 5.25 V (5 V nominal)
Gehäuse PDIP-40 (Plastic DIP, 40-pin) —
Betriebstemperatur 0C to +70C (commercial) -40 C to +85 C (industrial)
Montageart Through-Hole Through-Hole
Process Technology CMOS (UV-erasable) —
RoHS-Status [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS status]
Programming Method UV-erase + Altera programmer (legacy) —
Programmable Polarity Yes (user-configurable output) —
Output Enable Control Yes (per-pin three-state) —
Product Type — EPLD (Erasable Programmable Logic Device)
Family — Altera Classic EPLD
Macrocells — 24
Usable Gates — 480
Dedicated Inputs — 10
Register (Clock-to-Output) Delay — 20 ns
Technology — CMOS, UV-erasable (windowed ceramic)
Package Type — 40-pin PDIP (ceramic windowed)
Programming — Altera Classic device programmer / MAX+PLUS II flow
Lead-Free — [DATA_NEEDED: lead-free status]

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