EP910PI-40 vs EP910PI-30T Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EP910PI-40 disebabkan oleh Altera dan EP910PI-30T disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Altera
EP910PI-40 EP910PI-40 - 24-Macrocell Classic EPLD, 43ns, PDIP-40 | Altera

EP910PI-40 - 24-Macrocell Classic EPLD, 43ns, PDIP-40 | Altera

EP910PI-40 ⚠ Bahagian terakhir untuk beli

Pengandingan Spesifikasi

Parametr EP910PI-40 EP910PI-30T
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Masa Terakhir Dibeli Obsolete
Device Family Classic EPLD —
Part Number EP910PI-40 —
Architecture PAL-type macrocell, CMOS, UV-erasable —
Number of Macrocells 24 —
Number of Dedicated Inputs 12 —
Number of I/O Lines 24 —
External Clock Inputs 2 —
Frekuensi Klock Maksimum 25 MHz —
Propagation Delay (tPD) 43 ns 30 ns
Speed Grade -40 (43 ns) —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) 4.75 V to 5.25 V (5 V nominal)
Kemasan PDIP-40 (Plastic DIP, 40-pin) —
Suhu Operasi 0C to +70C (commercial) -40 C to +85 C (industrial)
Jenis Pemasangan Through-Hole Through-Hole
Process Technology CMOS (UV-erasable) —
Status RoHS [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS status]
Programming Method UV-erase + Altera programmer (legacy) —
Programmable Polarity Yes (user-configurable output) —
Output Enable Control Yes (per-pin three-state) —
Product Type — EPLD (Erasable Programmable Logic Device)
Family — Altera Classic EPLD
Macrocells — 24
Usable Gates — 480
Dedicated Inputs — 10
Register (Clock-to-Output) Delay — 20 ns
Technology — CMOS, UV-erasable (windowed ceramic)
Package Type — 40-pin PDIP (ceramic windowed)
Programming — Altera Classic device programmer / MAX+PLUS II flow
Lead-Free — [DATA_NEEDED: lead-free status]

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