EPC1441PCB vs EPC1213PC8 Vergleich
Detaillierter Direktvergleich von EPC1441PCB von Altera und EPC1213PC8 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPC1441PCB | EPC1213PC8 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | Memory ICs |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $2,18 | $10,95 |
| Device Type | Enhanced Configuration Device for SRAM FPGAs | — |
| Memory Density | 4,435,200 bits (~4 Mb) | — |
| Supported FPGA Families | ACEX 1K, APEX 20K, APEX II, FLEX 10K, FLEX 6000, FLEX 8000, Mercury | — |
| Programmability | In-system programmable via JTAG (IEEE 1149.1) | One-Time Programmable (OTP) |
| Configuration Interface | Altera serial/parallel configuration bus (nSTATUS, nCONFIG, DCLK, DATA) | — |
| Supply Voltage (VCC) | 3.3 V nominal | — |
| I/O Voltage Tolerance | 5 V tolerant | — |
| Gehäuse | PLCC-20 (Plastic Leaded Chip Carrier) | 8-Pin PDIP (R-PDIP-T8) |
| Montageart | Surface Mount / Socket | Through-Hole |
| Betriebstemperatur | 0 C to +70 C (commercial) | 0 °C to +70 °C (Commercial) |
| Configuration Mode | Automatic at power-up | — |
| Architecture | Flash memory + on-chip configuration controller | — |
| JTAG Support | Yes (IEEE 1149.1 boundary scan) | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | Compliant (post-lead-free Altera revision) |
| Lead-Free | [DATA_NEEDED: lead-free status] | Yes |
| Speichertyp | — | OTP Configuration PROM (EEPROM cell) |
| Speichergröße | — | 212 Kbit |
| Schnittstelle | — | Serial (4-wire: nCS, DCLK, DATA, OE) |
| Configuration Mode Supported | — | FLEX/APEX FPP / PS serial |
| Maximale Taktfrequenz | — | 6 MHz |
| Versorgungsspannung | — | 3.0 V to 3.6 V |
| Programming Standard | — | IEEE Std 1532 / Jam STAPL |
| Standby Current | — | < 50 µA typical |
| Pin-Anzahl | — | 8 |
| JEDEC Package Code | — | R-PDIP-T8 |