EPC1441PCB vs EPC1213PC8 比較

詳細並排比較 EPC1441PCB 由 Altera 與 EPC1213PC8 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPC1441PCB EPC1213PC8
品牌 Altera Altera
類別 FPGA & CPLD Memory ICs
生命週期狀態 Obsolete Obsolete
Device Type Enhanced Configuration Device for SRAM FPGAs —
Memory Density 4,435,200 bits (~4 Mb) —
Supported FPGA Families ACEX 1K, APEX 20K, APEX II, FLEX 10K, FLEX 6000, FLEX 8000, Mercury —
Programmability In-system programmable via JTAG (IEEE 1149.1) One-Time Programmable (OTP)
Configuration Interface Altera serial/parallel configuration bus (nSTATUS, nCONFIG, DCLK, DATA) —
Supply Voltage (VCC) 3.3 V nominal —
I/O Voltage Tolerance 5 V tolerant —
封裝 PLCC-20 (Plastic Leaded Chip Carrier) 8-Pin PDIP (R-PDIP-T8)
安裝類型 Surface Mount / Socket Through-Hole
工作溫度 0 C to +70 C (commercial) 0 °C to +70 °C (Commercial)
Configuration Mode Automatic at power-up —
Architecture Flash memory + on-chip configuration controller —
JTAG Support Yes (IEEE 1149.1 boundary scan) —
RoHS 狀態 [DATA_NEEDED: RoHS compliance status] Compliant (post-lead-free Altera revision)
Lead-Free [DATA_NEEDED: lead-free status] Yes
記憶體類型 — OTP Configuration PROM (EEPROM cell)
記憶體容量 — 212 Kbit
介面 — Serial (4-wire: nCS, DCLK, DATA, OE)
Configuration Mode Supported — FLEX/APEX FPP / PS serial
最大時脈頻率 — 6 MHz
供應電壓 — 3.0 V to 3.6 V
Programming Standard — IEEE Std 1532 / Jam STAPL
Standby Current — < 50 µA typical
腳位數 — 8
JEDEC Package Code — R-PDIP-T8

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