EPC16QC100N vs EPC16SI16N Vergleich
Detaillierter Direktvergleich von EPC16QC100N von Altera und EPC16SI16N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EPC16SI16N - 16Mb Enhanced Configuration Device, 16-SOIC | Altera / Intel
EPC16SI16N ⚠ Letzte BestellmöglichkeitSpezifikationsvergleich
| Parameter | EPC16QC100N | EPC16SI16N |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | Memory ICs | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Letzte Kaufgelegenheit |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $24,10 | $4,35 |
| Speichergröße | 16 Mbit (16,777,216 bits) | 16 Mb (16,777,216 bits) |
| Programmable Type | In System Programmable | — |
| Configuration Clock Frequency | 33 MHz max | — |
| On-Chip Decompression | Yes (supports compressed bitstreams) | — |
| Supply Voltage (VCC) | 3.0 V to 3.6 V | — |
| Access Time | 90 ns typical | — |
| Flash Read Bandwidth | 160 Mbps (16-bit DQ at 10 MHz) | — |
| Configuration Interface | FPP / PS / AS via dedicated FPGA pins | — |
| JTAG (IEEE 1149.1) ISP | Supported | — |
| Betriebstemperatur | 0 C to 70 C | -40 C to +85 C (industrial, 'SI' suffix) |
| Gehäuse | 100-pin PQFP (20 x 14 mm) | 16-pin SOIC (300 mil, 'SI' suffix) |
| Montageart | Surface Mount | Surface Mount |
| Lead Free | Yes (per datasheet) | — |
| Packaging | Tray | — |
| Supported FPGA Families | ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX | — |
| Speichertyp | — | Non-volatile flash (enhanced configuration device) |
| Schnittstelle | — | Altera enhanced serial configuration (DCLK, DATA, nCS, nRESET, nSTATUS) |
| Programming Interface | — | JTAG (IEEE 1149.1 boundary scan) |
| Maximum Operating Frequency | — | 40 MHz (fast configuration mode) |
| Betriebsversorgungsspannung | — | 3.3 V (typ) |
| Lead-Free / Finish | — | Lead-free (matte tin), 'N' suffix |
| MSL-Level | — | [DATA_NEEDED: MSL level] |
| RoHS-Status | — | Compliant |
| In-System Programmability | — | Yes (via JTAG, multiple reprogramming cycles) |
| Compatible FPGA Series | — | Altera Stratix II, Stratix III, Cyclone, Cyclone II, Cyclone III |
| Configuration Daisy-Chaining | — | Supported (multiple devices / multiple FPGAs) |
| On-Chip Charge Pump | — | Integrated (no external VPP required) |