EPC16QC100N vs EPC16SI16N 对比

详细并排对比 EPC16QC100N 出自 Altera 和 EPC16SI16N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPC16QC100N EPC16SI16N
品牌 Altera Intel
分类 Memory ICs FPGA & CPLD
生命周期状态 Obsolete 最后采购期
库存状态 有库存 有库存
单价(USD) $24.10 $4.35
存储容量 16 Mbit (16,777,216 bits) 16 Mb (16,777,216 bits)
Programmable Type In System Programmable —
Configuration Clock Frequency 33 MHz max —
On-Chip Decompression Yes (supports compressed bitstreams) —
Supply Voltage (VCC) 3.0 V to 3.6 V —
Access Time 90 ns typical —
Flash Read Bandwidth 160 Mbps (16-bit DQ at 10 MHz) —
Configuration Interface FPP / PS / AS via dedicated FPGA pins —
JTAG (IEEE 1149.1) ISP Supported —
工作温度 0 C to 70 C -40 C to +85 C (industrial, 'SI' suffix)
封装 100-pin PQFP (20 x 14 mm) 16-pin SOIC (300 mil, 'SI' suffix)
安装类型 Surface Mount Surface Mount
Lead Free Yes (per datasheet) —
Packaging Tray —
Supported FPGA Families ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX —
存储器类型 — Non-volatile flash (enhanced configuration device)
接口 — Altera enhanced serial configuration (DCLK, DATA, nCS, nRESET, nSTATUS)
Programming Interface — JTAG (IEEE 1149.1 boundary scan)
Maximum Operating Frequency — 40 MHz (fast configuration mode)
工作电源电压 — 3.3 V (typ)
Lead-Free / Finish — Lead-free (matte tin), 'N' suffix
MSL 等级 — [DATA_NEEDED: MSL level]
RoHS 状态 — Compliant
In-System Programmability — Yes (via JTAG, multiple reprogramming cycles)
Compatible FPGA Series — Altera Stratix II, Stratix III, Cyclone, Cyclone II, Cyclone III
Configuration Daisy-Chaining — Supported (multiple devices / multiple FPGAs)
On-Chip Charge Pump — Integrated (no external VPP required)

数据手册与资源

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